Generation or conversion of analog audio from a source of digital audio by conventional methods typically involves a choice between higher fidelity (with increased cost and increased power consumption) or lower cost and lower power consumption (with lower fidelity).
Higher fidelity audio can be achieved in converting digital audio to analog by including a higher performance Phase Locked Loop (PLL) for driving or clocking sensitive audio processing electronic circuitry. A higher performance PLL provides a clocking signal with a reduced amount of clock signal jitter compared to a low performance PLL. However, the reduced clock signal jitter provided by the higher performance PLL comes at the expense of increased cost and increased power consumption. The increased cost and power consumption associated with a higher performance PLL are a result of a need for an increased amount of semiconductor circuitry and “real estate.” Furthermore, increased power consumption negatively impacts the amount of time a battery can supply electrical power to an electronic device containing a higher performance PLL. In contrast, cost and power consumption can be decreased by using a lower performance PLL. However, the lower cost and lower power consumption results in producing audio with lower fidelity.
PLLs are versatile electronic components that can be configured to generate a wide array of clock signals for driving electronic circuitry. A PLL may function to convert an input clock signal with a corresponding frequency into a clock signal having an altogether different corresponding frequency. A PLL may be adept at creating a clock signal with a precise frequency, however, the clock signal created by the PLL may also exhibit jitter. Jitter is the deviation in some aspect (i.e. phase, amplitude, or width) of the pulses in a digital signal. The jitter exhibited by PLLs is inherent to the design of PLLs and can be reduced, but at the expense of increased circuitry, power consumption and complexity.
Digital audio equipment is generally configured to convert digital or discrete audio information to an analog signal for transmission to and reception by a human ear.
In general, the process for converting the digital audio information into an analog signal includes the use of a Digital-to-Analog Converter (DAC). A DAC typically operates to convert a digital signal into a proportional amount of electrical voltage or current as represented by the digital signal. Quantization error or noise is inherent in DACs and is a result of the finite resolution provided by DACs. The accuracy of the conversion of digital information to analog by a DAC is further impacted by clock signal jitter resident in the signal used to clock or drive the DAC. A low amount of clock signal jitter corresponds to increased accuracy and an increased signal-to-noise ratio in converting the digital audio information to its analog representation. Conversely, a higher amount of clock signal jitter corresponds to lower accuracy and a lower signal-to-noise ratio in converting the digital audio information to its analog representation.
FIGS. 1-7 will now be presented in order to further illustrate issues related to converting digital audio to its analog representation.
FIG. 1 illustrates a conventional circuit for converting digital audio information to its analog representation.
A circuit 100 includes a crystal 102, a digital oscillator 106, an audio PLL 110, a system PLL 114, a compressed digital audio source 116, a digital audio decompression portion 118, an audio signal generator portion 120, an interpolator 122, a noise shaping portion 126 and a DAC 130. In this illustration, each of digital oscillator 106, audio PLL 110, system PLL 114, compressed digital audio source 116, digital audio decompression portion 118, audio signal generator portion 120, interpolator 122, noise shaping portion 126 and DAC 130 are illustrated as distinct devices. However, at least one of digital oscillator 106, audio PLL 110, system PLL 114, compressed digital audio source 116, digital audio decompression portion 118, audio signal generator portion 120, interpolator 122, noise shaping portion 126 and DAC 130 may be combined as a unitary device.
Crystal 102 is operable to generate an electrical signal 104. Digital oscillator 106 is arranged to output a reference clock signal 108 based on electrical signal 104. In this example, digital oscillator 106 is arranged to receive electrical signal 104 directly from crystal 102. Alternatively, intermediate circuitry may be included to modify electrical signal 104 prior to digital oscillator 106. Non-limiting examples of intermediate circuitry include matching networks, amplifiers, filters, resistors, etc.
Audio PLL 110 is arranged to output an audio clock signal 112 based on reference clock signal 108. In this example, audio PLL 110 is arranged to receive reference clock signal 108 directly from digital oscillator 106. Alternatively, intermediate circuitry may be included to modify reference clock signal 108 prior to audio PLL 110.
System PLL 114 is arranged to output a system clock signal 115 based on reference clock signal 108. In this example, system PLL 114 is arranged to receive reference clock signal 108 directly from digital oscillator 106. Alternatively, intermediate circuitry may be included to modify reference clock signal 108 prior to system PLL 114.
Compressed digital audio source 116 is arranged to output a compressed digital audio signal 117 based on system clock signal 115. In this example, compressed digital audio source 116 is arranged to receive system clock signal 115 directly from system PLL 114. Alternatively, intermediate circuitry may be included to modify system clock signal 115 prior to compressed digital audio source 116.
Digital audio decompression portion 118 is arranged to output a decompressed digital audio signal 119 based on system clock signal 115 and compressed digital audio signal 117. In this example, digital audio decompression portion 118 is arranged to receive system clock signal 115 directly from system PLL 114 and to receive compressed digital audio signal 117 directly from compressed digital audio source 116. Alternatively, intermediate circuitry may be included to modify at least one of system clock signal 115 and compressed digital audio signal 117 prior to digital audio decompression portion 118.
Audio signal generator portion 120 is arranged to output a digital audio signal 121 based on audio clock signal 112 and decompressed digital audio signal 119. In this example, audio signal generator portion 120 is arranged to receive audio clock signal 112 directly from audio PLL 110 and to receive decompressed digital audio signal 119 directly from digital audio decompression portion 118. Alternatively, intermediate circuitry may be included to modify at least one of audio clock signal 112 and decompressed digital audio signal 119 prior to audio signal generator portion 120.
Interpolator 122 is arranged to output an interpolated signal 124 based on digital audio signal 121. In this example, interpolator 122 is arranged to receive digital audio signal 121 directly from audio signal generator portion 120. Alternatively, intermediate circuitry may be included to modify digital audio signal 121 prior to interpolator 122.
Noise shaping portion 126 is arranged to output a shaped signal 128 based interpolated signal 124. In this example, noise shaping portion 126 is arranged to receive interpolated signal 124 directly from interpolator 122. Alternatively, intermediate circuitry may be included to modify interpolated signal 124 prior to noise shaping portion 126.
DAC 130 is arranged to output an analog signal 132 based on audio clock signal 112 and shaped signal 128. In this example, DAC 130 is arranged to receive audio clock signal 112 directly from audio PLL 110 and to receive shaped signal 128 directly from noise shaping portion 126. Alternatively, intermediate circuitry may be included to modify at least one of audio clock signal 112 and shaped signal 128 prior to DAC 130.
Crystal 102 generates electrical signal 104 so as to have a very precise frequency. However, the frequency of electrical signal 104 is typically limited as a result of the capacitance and inductance of semiconductor packaging devices. A too high frequency for electrical signal 104 may be distorted by the capacitance and inductance of a semiconductor package. Accordingly, the frequency of electrical signal 104 is typically of a lower frequency and stepped up internally within a semiconductor device using a PLL, as the capacitance and inductance resident within a semiconductor device is typically much less than the capacitance and inductance of a semiconductor package. The lower capacitance and inductance resident within a semiconductor device, as compared to the semiconductor packaging, allows for generating very high clock signal frequencies internal to a semiconductor device using a PLL. However, the high frequency clock signal comes at the expense of increased clock signal jitter.
In this case, digital oscillator 106 acts as a frequency converter and generates reference clock signal 108 in a manner appropriate for reception by other associated electronic components.
Audio PLL 110 converts reference clock signal 108 into audio clock signal 112 having a different frequency from reference clock signal 108. Typically, audio PLL 110 is programmable, such that the frequency of audio clock signal 112 may be changed as desired. Furthermore, the frequency of audio clock signal 112 is typically a higher frequency than the frequency of reference clock signal 108.
System PLL 114 converts reference clock signal 108 into system clock signal 115 having a different frequency from reference clock signal 108. Typically, system PLL 114 is programmable, such that the frequency of system clock signal 115 may be changed as desired. Furthermore, the frequency of system clock signal 115 is typically a higher frequency than the frequency of reference clock signal 108.
Compressed digital audio source 116 is a source of compressed digital audio data, (e.g., music). Non-limiting examples sources of digital audio include random access memory (RAM), read-only memory (ROM), compact disk (CD), digital video disk (DVD) and hard disk. Digital audio is typically compressed in order to reduce the amount of storage space required for storage and to reduce the amount of bandwidth required for transmitting and receiving the digital audio.
Digital audio decompression portion 118 converts compressed digital audio to uncompressed digital audio. Non-limiting examples of compressed digital audio formats include MP3, AAC and AC3. Decompression of digital audio requires a significant amount of computational processing. This increased computational processing may require system clock signal 115 to operate at a significantly higher frequency than the frequency at which the digital audio is sampled. Typically, digital audio decompression portion 118 may not operate at the reduced clock frequency of audio clock signal 112, as it would not provide digital audio decompression portion 118 enough computational processing power for decompressing a source of compressed audio.
Audio signal generator portion 120 processes a decompressed audio signal such that it can be processed by circuitry operating at a reduced clock frequency to support further processing of a digital audio signal. Audio signal generator portion 120 outputs the digital audio data as digital audio signal 121 in synchronization with audio clock signal 112, as will be discussed in more detail below.
The digital audio information to be supplied by circuit 100 may need to have a higher frequency than the frequency of digital audio signal 121. Interpolator 122 creates digital audio information, which is an estimate based on digital audio signal 121. For example, audio data within digital audio signal 121 might have been sampled at a frequency of 8 KHz, whereas the audio data to be supplied by circuit 100 might be required to have a sampling frequency of 16 KHz. Interpolator 122 may function to insert estimated audio data between the actual sampled audio data within digital audio signal 121 to generate interpolated signal 124.
Noise shaping portion 126 removes high frequency portions of interpolated signal 124 to reduce distortion within interpolated signal 124 to generate shaped signal 128.
DAC 130 converts shaped signal 128, which is a digital signal, to analog signal 132, to be output by circuit 100.
Typically, when generating higher fidelity audio, audio PLL 110 is configured as a higher performance PLL, which produces audio clock signal 112 with a lowered amount of clock signal jitter. The lower amount of clock signal jitter provided by audio PLL 110 is realized through increased electronic circuitry, which results in increased costs and increased power consumption. In contrast to audio PLL 110, system PLL 114 is a lower quality PLL with an increased amount of clock signal jitter. However, since digital audio decompression portion 118 is less sensitive to clock signal jitter, the lower quality system PLL 114 is sufficiently capable of driving digital audio decompression portion 118. Furthermore, since system. PLL 114 is a lower performance PLL, its cost and power consumption is relatively lower than the cost and power consumption of the higher performance audio PLL 110.
Another conventional method for increasing the fidelity when converting a digital audio signal to an analog audio signal involves driving or clocking, sensitive audio circuitry directly from a digital oscillator. The digital oscillator provides a clock signal with a lower amount of clock signal jitter, cost and power dissipation as compared to a PLL, but at the expense of a lower clock signal frequency than provided by a PLL.
FIG. 2 illustrates a circuit 200, a conventional circuit for converting digital audio information to analog similar to FIG. 1 except with a PLL component removed and the clock signal for the audio processing portion of the circuit driven by a digital oscillator instead of by a PLL.
As illustrated in FIG. 2, audio PLL 110 which was included in FIG. 1 is not included in FIG. 2. As shown in FIG. 2, reference clock signal 108 is directly provided to audio signal generator portion 120 and DAC 130.
The clock signal frequency of audio clock signal 112 as supplied by audio PLL 110 in FIG. 1 is higher than the clock signal frequency of reference clock signal 108 supplied by digital oscillator 106 in FIG. 2. As will be demonstrated in further discussion, the lower clock signal frequency of reference clock signal 108 supplied by digital oscillator 106 to audio signal generator portion 120 and DAC 130 in FIG. 2 results in an increased amount of noise over the amount of noise as produced by the circuit in FIG. 1. The increased amount of noise produced in FIG. 2 decreases the signal-to-noise ratio and fidelity of the output analog signal as compared to that of FIG. 1.
A discussion associated with an ideal versus an actual audio signal will now be presented with respect to FIG. 3 for further comparing and contrasting the conventional circuits of FIG. 1 and FIG. 2.
FIG. 3 illustrates waveforms associated with circuit 100 of FIG. 1 and circuit 200 of FIG. 2.
FIG. 3 includes a waveform 300, a waveform 302 and a waveform 304. Waveform 300 represents an example ideal output signal for analog signal 132 from DAC 130. Waveform 302 represents an example actual output signal for analog signal 132 from DAC 130. Waveform 304 represents an example error waveform, the difference between waveform 300 and waveform 302.
An x-axis 306, which is shared by each of waveform 300, waveform 302 and waveform 304, represents units of time. A y-axis 307 represents voltage.
Waveform 300 starts at time t0 and includes a pulse 308, a pulse 310 and a pulse 312. Pulse 308 is positive in voltage and has a rising edge 314 at time t2 and a falling edge 316 at time t3. Pulse 310 is positive in voltage and has a rising edge 318 at time t5 and a falling edge 320 at time t7. Pulse 312 is positive in voltage and has a rising edge 322 at time t10 and a falling edge 324 at time t12.
Waveform 302 starts at time t0 and includes a pulse 326, a pulse 328 and a pulse 330. Pulse 326 is positive in voltage and has a rising edge 332 at time t1 and a falling edge 334 at time t4. Pulse 328 is positive in voltage and has a rising edge 336 at time t6 and a falling edge 338 at time t8. Pulse 330 is positive in voltage and has a rising edge 340 at time t9 and a falling edge 342 at time t11.
Waveform 304 starts at time t0 and includes a pulse 344, a pulse 346, a pulse 348, a pulse 350, a pulse 352 and a pulse 354. Pulse 344 is positive in voltage and has a rising edge 356 at time t1 and a falling edge 358 at time t2. Pulse 346 is positive in voltage and has a rising edge 360 at time t3 and a falling edge 362 at time t4. Pulse 348 is negative in voltage and has a falling edge 364 at time t5 and a rising edge 366 at time t6. Pulse 350 is positive in voltage and has a rising edge 368 at time t7 and a falling edge 370 at time t8. Pulse 352 is positive in voltage and has a rising edge 372 at time t9 and a falling edge 374 at time t10. Pulse 354 is negative in voltage and has a falling edge 376 at time t11 and a rising edge 378 at time t12.
Waveform 304 is the difference between waveform 300 and waveform 302 and represents the error between an ideal example output signal for analog signal 132 from DAC 130 and an actual example output signal for analog signal 132 from DAC 130. In this example, a positive pulse voltage in waveform 304 indicates that the ideal output signal for analog signal 132 from DAC 130 is a binary LOW whereas the actual example output signal for analog signal 132 from DAC 1.30 is a binary HIGH. Similarly, in this example, a negative pulse voltage in waveform 304 indicates that the ideal output signal for analog signal 132 from DAC 130 is a binary HIGH whereas the actual example output signal for analog signal 132 from DAC 130 is a binary LOW.
Between time t0 and time t1, the ideal DAC output as illustrated in waveform 300 is a binary LOW and the actual DAC output as illustrated in waveform 302 is also a binary LOW. Therefore, the difference between waveform 300 and waveform 302 during the time period between time t0 and time t1 results in a binary LOW in waveform 304. Between time t1 and time t2, the ideal DAC output as illustrated in waveform 300 is a binary LOW, whereas the actual DAC output as illustrated in waveform 302 is a binary HIGH. This discrepancy may take place for any number of reasons, which is not the focus of this discussion. For purposes of this discussion, presume that a discrepancy exists nonetheless. Here, the difference between waveform 300 and waveform 302 during the time period between time t1 and time t2 results in pulse 344, which is positive in voltage to indicate a positive difference. Between time t2 and time t3, the ideal DAC output as illustrated in waveform 300 is a binary HIGH and the actual DAC output as illustrated in waveform 302 is also a binary HIGH. Therefore, the difference between waveform 300 and waveform 302 during the time period between time t2 and time t3 results in a binary LOW in waveform 304.
To simplify the discussion, the above analysis of waveform 300, waveform 302 and waveform 304 for the time periods at or around pulse 344 may be used to analyze time periods at or around pulses 346, 350 and 352.
Between time t4 and time t5, the ideal DAC output as illustrated in waveform 300 is a binary LOW and the actual DAC output as illustrated in waveform 302 is also a binary LOW. Therefore, the difference between waveform 300 and waveform 302 during the time period between time t4 and time t5 results in a binary LOW in waveform 304. Between time t5 and time t6, the ideal DAC output as illustrated in waveform 300 is a binary HIGH, whereas the actual DAC output as illustrated in waveform 302 is a binary LOW. This discrepancy may take place for any number of reasons, which is not the focus of this discussion. For purposes of this discussion, presume that a discrepancy exists nonetheless. Here, the difference between waveform 300 and waveform 302 during the time period between time t5 and time t6 results in pulse 348, which is negative in voltage to indicate a negative difference. Between time t6 and time t7, the ideal DAC output as illustrated in waveform 300 is a binary HIGH and the actual DAC output as illustrated in waveform 302 is also a binary HIGH. Therefore, the difference between waveform 300 and waveform 302 during the time period between time t2 and time t3 results in a binary LOW in waveform 304.
To simplify the discussion, the above analysis of waveform 300, waveform 302 and waveform 304 for the time periods at or around pulse 348 may be used to analyze time periods at or around pulse 354.
Waveform 300 represents the desired signal output of analog signal 132, ie., a perfect rendition of the audio signal. However, due to clock signal jitter and other effects, the actual output of analog signal is waveform 302. If the reproduction of the audio signal were performed perfectly, waveform 300 and waveform 302 would be identical and thus waveform 304 would appear as a binary LOW line. However, in practicality, the error in the actual signal may be measured as pulses 344, 346, 348, 350, 352 and 354.
A further discussion associated with an ideal versus an actual audio signal will now be presented in FIG. 4 for further comparing and contrasting the conventional circuits of FIG. 1 and FIG. 2 and the conventional waveforms of FIG. 3.
FIG. 4A illustrates a conventional frequency spectrum graph as generated by the conventional circuits of FIG. 1 and FIG. 2 and waveform 300 of FIG. 3.
FIG. 4A illustrates an ideal DAC frequency spectrum 402 of a signal x(n) where x represents a digital audio signal amplitude sampled at a discrete time period n. For example, x(n) may be represented as x(0), x(1), x(2) . . . .
FIG. 4A has a y-axis 410 with dimensions of magnitude and units of volts squared and an x-axis 412 with dimensions of frequency and units of Hertz. The frequency range for x-axis 412 includes frequencies from 0 Hz increasing up to the frequency used to sample the audio divided by 2 which is denoted as a divided sample frequency 414.
An output signal spectrum 416 is located at a signal frequency 418 of x-axis 412. A cycle-to-cycle noise frequency spectrum 422 initiates at a cutoff frequency 420 located on x-axis 412 and increases monotonically until it terminates at divided sample frequency 414 on x-axis 412. Cycle-to-cycle noise is the average difference in length of any two adjacent cycles.
FIG. 4B illustrates a conventional frequency spectrum graph as generated by the conventional circuits of FIG. 1 and FIG. 2 and waveform 302 of FIG. 3.
FIG. 4B illustrates a jitter error frequency spectrum 404 of a signal x(n)−x(n−1), where x(n) represents a digital audiosignal amplitude and x(n−1) represents the audio signal x delayed by one sample. FIG. 4B demonstrates the negative results of experiencing jitter in converting a digital audio signal to an analog signal.
FIG. 4B has a y-axis 424 with dimensions of magnitude and units of volts squared and an x-axis 426 with dimension of frequency and units of Hertz. The frequency range for x-axis 426 includes frequencies from 0 Hertz increasing up to the frequency used to sample the audio divided by 2 which is denoted as a divided sample frequency 428.
An output signal spectrum 430 is located at a signal frequency 432 of x-axis 426. A jitter noise frequency spectrum 436 initiates at a cutoff frequency 434 located on x-axis 426 and increases in a monotonic fashion until it terminates at divided sample frequency 428 on x-axis 426.
As illustrated in FIG. 4A-B, clock signal jitter induced into a digital audio circuit increases the relative magnitude of jitter noise frequency spectrum 436 as compared to output signal spectrum 430, both shown in FIG. 4B, and is significantly larger than the relative magnitude of cycle-to-cycle noise frequency spectrum 422 as compared to output signal spectrum 416 shown in FIG. 4A. As a result of induced clock signal jitter, the signal-to-noise ratio as demonstrated in FIG. 4B is significantly less than the signal-to-noise ratio as shown in FIG. 4A. The audio as depicted by FIG. 4B has less quality and fidelity due to increased clock signal jitter than the audio as illustrated in FIG. 4A. The more clock signal jitter induced, the more the audio of FIG. 4B is degraded when compared to the audio of FIG. 4A. Similarly, the more waveform 302 and waveform 300 of FIG. 3 are different as indicated by waveform 304 of FIG. 3, the more clock signal jitter is induced, resulting in increased degradation of the resulting analog audio signal. For example, the larger the clock signal error or clock difference between waveform 300 and waveform 302 of FIG. 3, the lower the signal-to-noise ratio of FIG. 4B which corresponds to a lower fidelity digital audio to analog conversion.
FIG. 4C illustrates a clock error frequency spectrum as generated by the conventional circuits of FIG. 1 and FIG. 2 and waveform 302 of FIG. 3.
FIG. 4C illustrates a clock signal error frequency spectrum 406. Clock signal error frequency spectrum 406 may be represented as the frequency spectrum of the clock signal jitter, Δt, divided by the period of the clock signal, Tclk. FIG. 4C demonstrates the frequency spectrum of error in a clock signal.
FIG. 4C has a y-axis 438 with dimensions of magnitude and units of volts squared and an x-axis 440 with dimensions of frequency and units of Hertz. The frequency range for x-axis 440 includes frequencies from 0 Hertz increasing up to the frequency used to sample the audio divided by 2 which is denoted as a divided sample frequency 442.
Long term, or accumulated, jitter is the change in a clock signal's output from the ideal position, measured over several consecutive cycles. A long term jitter noise frequency spectrum 444 is located in the range from 0 Hertz up to a cutoff frequency 446. Long term jitter noise frequency spectrum 444 has a maximum magnitude at a maximum 448. A cycle-to-cycle noise frequency spectrum 450 extends from cutoff frequency 446 on x-axis 440 up to divided sample frequency 442 on x-axis 440. Cycle-to-cycle noise frequency spectrum 450 decreases monotonically from cutoff frequency 446 on x-axis 440 up to a cutoff frequency 452 on x-axis 440. The magnitude of cycle-to-cycle noise frequency spectrum 450 is flat from cutoff frequency 452 on x-axis 440 up to divided sample frequency 442 on x-axis.
FIG. 4C illustrates how the frequency spectrum of long term jitter noise as denoted by long term jitter noise frequency spectrum 444 has a predominate impact on audio quality as compared to the frequency spectrum of cycle-to-cycle noise as depicted by cycle-to-cycle noise frequency spectrum 450. The frequency spectrum of long term jitter noise is located in the audio frequency spectrum, as denoted by frequencies less than cutoff frequency 446. On the contrary, the frequency spectrum of cycle-to-cycle noise is located outside of the audio frequency spectrum, as denoted by frequencies greater than cutoff frequency 446.
FIG. 4D illustrates a noise frequency spectrum 408 of digital signal e(n), where e(n) represents value of error at a discrete time n. The signal e(n) may be represented as the jitter signal x(n)−x(n−1) as depicted in the frequency domain in FIG. 4B multiplied by the clock signal error Δt/Tclk as depicted in the frequency domain in FIG. 4C as shown below:e(n)=(x(n)−x(n−1))·(Δt(n)/Tclk).
Multiplication of two signals in the time domain may be represented in the frequency domain by performing a mathematical convolution of the two frequency domain representations of the signals. Performing a convolution of the frequency domain representations of (x(n)−x(n−1)) and (Δt(n)/Tclk) in results in the following equation:E(z)=((1−z−1)·X(z))·FclkPn(z).
The symbol  above represents convolution of ((1−z−1)·X(z))·Fclk with Pn(z) to generate E(z), where E(z) represents conversion of e(n) to the frequency domain, ((1−z−1)·X(z)) represents the conversion of (x(n)−x(n−1)) to the frequency domain, Fclk represents conversion of 1/Tclk to the frequency domain and Pn(z) represents conversion of Δt(n) to the frequency domain. Performing the convolution operation above may also be represented as convolving jitter error frequency spectrum 404 of FIG. 4B with clock signal error frequency spectrum 406 of FIG. 4C. Noise frequency spectrum 408 of FIG. 4D represents the result of the operation of convolving FIG. 4B with FIG. 4C.
FIG. 4D illustrates why using a lower frequency clock for generation of analog audio as illustrated by reference clock signal 108 in FIG. 2 results in poorer quality audio over the configuration as illustrated when using audio clock signal 112 in FIG. 1 for generation of analog audio, even though the clock signal jitter produced by reference clock signal 108 of FIG. 2 is less than the clock signal jitter produced by audio clock signal 112 of FIG. 1. In performing the convolution of FIG. 4B with FIG. 4C, it is demonstrated that the lower the clock signal frequency, the more the long term jitter noise frequency spectrum 444 of FIG. 4C becomes a negative factor, i.e. less signal-to-noise ratio and less fidelity, in the audio frequency spectrum as denoted by frequencies less than a cutoff frequency.
FIG. 4D has a y-axis 454 with dimensions of magnitude and units of volts squared and an x-axis 456 with dimensions of frequency and units of Hz. The frequency range for x-axis 456 includes frequencies from 0 Hz increasing up to the frequency used to sample the audio divided by 2 which is denoted as a divided sample frequency 458.
A noise skirt frequency spectrum 460 initiates at a frequency of 0 Hz on x-axis 456 and terminates as a cutoff frequency 462 on x-axis 456. Noise skirt frequency spectrum 460 has a maximum magnitude at a maximum 464. A jitter noise frequency spectrum 466 initiates at cutoff frequency 462 and increases monotonically until it reaches divided sample frequency 458 on x-axis 456. A noise floor 468 is located at cutoff frequency 462.
Ideal DAC frequency spectrum 402 of FIG. 4A represents a frequency spectrum for a perfect rendition of a digital audio signal as presented by waveform 300 as illustrated in FIG. 3. However, due to errors induced as a result of clock signal jitter in the conversion of the digital audio information to analog as produced by the conventional circuits of FIG. 1 and FIG. 2 and as illustrated in FIG. 3 by waveform 300, waveform 302 and waveform 304, the actual audio spectrum generated include the effects of jitter is illustrated in FIG. 4B.
As illustrated in FIG. 4A-B, the magnitude of output signal spectrum 430 of FIG. 4B is less than the magnitude of output signal spectrum 416 of FIG. 4A. Furthermore, jitter noise frequency spectrum 436 of FIG. 4B is a larger magnitude than that of cycle-to-cycle noise frequency spectrum 422 of FIG. 4A. As a result, the signal-to-noise ratio for ideal DAC frequency spectrum 402 of FIG. 4A is greater than the signal-to-noise ratio of jitter error frequency spectrum 404 of FIG. 4B. The cause of the degraded signal-to-noise ratio of jitter error frequency spectrum 404 as compared to ideal DAC frequency spectrum 402 is a result of experiencing clock signal jitter as discussed previously with respect to FIG. 1, FIG. 2 and FIG. 3.
Clock signal error frequency spectrum 406 represents the frequency spectrum as related to clock signal jitter. Clock signal error frequency spectrum 406 is basically composed of two elements: noise within the frequency band of interest, i.e. frequencies less than cutoff frequency 446, as represented by long term jitter noise frequency spectrum 444 and noise external to the frequency band of interest, i.e. frequencies less than cutoff frequency 446, as represented by cycle-to-cycle noise frequency spectrum 450.
In the time-domain, a signal and its respective jitter noise may be multiplied by any related clock signal noise to determine the resulting output of a circuit. A corresponding operation may be performed in the z-domain or frequency domain by performing a convolution of the frequency spectrum of the signal and its related jitter noise with the frequency spectrum of any related clock signal noise to realize the frequency spectrum for the output of a circuit. Noise frequency spectrum 408 of FIG. 4D is the result of performing a convolution of jitter error frequency spectrum 404 of FIG. 4B with clock signal error frequency spectrum 406 of FIG. 4C.
As illustrated by noise frequency spectrum 408 of FIG. 4D, noise skirt frequency spectrum 460 is present in the frequency band of interest resulting in the degradation of the signal-to-noise ratio of the output signal. Furthermore, the noise floor is elevated as illustrated by noise floor 468. The degradation in signal-to-noise ratio and the increase in the noise floor as illustrated by noise frequency spectrum 408 are a result of clock signal jitter.
A discussion associated with comparing the conventional circuits of FIG. 1 and FIG. 2 as related to clock signal phase noise will now be discussed with respect to FIG. 5.
FIG. 5 illustrates a graph of a comparison of phase noise versus frequency for the conventional circuits illustrated in FIG. 1 and FIG. 2.
A graph 500 includes a y-axis 502 with dimensions of phase noise and units of dB and an x-axis 504 with dimensions of frequency and units of Hertz.
A dashed line high frequency clock signal phase noise spectrum 506 initiates with a phase noise of approximately −100 dB at a frequency of 20 Hz on x-axis 504 and increases monotonically up to a dashed line maximum 508 with a phase noise of approximately −80 dB and at approximately a frequency of 10 KHz. Dashed line high frequency clock signal phase noise spectrum 506 decreases monotonically from approximately 10 KHz on x-axis 504 with a corresponding phase noise of approximately −78 dB to 20 KHz on x-axis 504 with a corresponding phase noise of approximately −79 dB.
A dotted line low frequency clock signal phase noise spectrum 510 initiates with a phase noise of approximately −20 dB at a frequency of 20 Hz on x-axis 504 and decreases monotonically to approximately 20 KHz on x-axis 504 with a corresponding phase noise of approximately −79 dB.
Dashed line high frequency clock signal phase noise spectrum 506 and dotted line low frequency clock signal phase noise spectrum 510 converge at a frequency of approximately 20 KHz on x-axis 504 with a corresponding phase noise on y-axis 502 of approximately −79 dB.
Dashed line high frequency clock signal phase noise spectrum 506 corresponds with the conventional circuit as illustrated in FIG. 1. Dotted line low frequency clock signal phase noise spectrum 510 corresponds to the conventional circuit as illustrated in FIG. 2.
As illustrated in FIG. 5, the phase noise for the convention circuit of FIG. 2 as illustrated by dotted line low frequency clock signal phase noise spectrum 510 is greater than the phase noise of the conventional circuit of FIG. 1 as illustrated by dashed line high frequency clock signal phase noise spectrum 506. Even though the clock signal jitter generated on reference clock signal 108 by digital oscillator 106 of FIG. 2 is less than the clock signal jitter generated on audio clock signal 112 by audio PLL 110 of FIG. 1, the phase noise generated by the circuit of FIG. 2 is greater than the phase noise generated by the circuit of FIG. 1. The increase in phase noise is a result of the lower clock signal frequency of reference clock signal 108 as generated by digital oscillator 106 of FIG. 1 as compared to the higher clock signal frequency of audio clock signal 112 as generated by audio PLL 110 in FIG. 2.
FIG. 6 illustrates a graph of a comparison of ideal audio signal spectrum versus frequency for the conventional circuits illustrated in FIG. 1 and FIG. 2.
FIG. 6 illustrates a graph of a comparison between using a low frequency clock signal versus a high frequency clock signal for an ideal audio signal spectrum.
A graph 600 includes a y-axis 602 with dimensions of magnitude and units of dB and a x-axis 604 with dimensions of frequency and units of Hz.
A dashed line high frequency clock signal noise spectrum 606 initiates at x-axis 604 frequency of 100 Hz and y-axis 602 magnitude of approximately −139 dB and increases monotonically to a dashed line maximum 608 located at x-axis 604 frequency of approximately 10 KHz and y-axis 602 magnitude of approximately −129 dB. Dashed line high frequency clock signal noise spectrum decreases monotonically from dashed line maximum 608 to x-axis 604 frequency of 20 KHz and a corresponding y-axis 602 magnitude of approximately −130 dB.
A dotted line low frequency clock signal noise spectrum 610 initiates at x-axis 604 frequency of 100 Hz and y-axis 602 magnitude of approximately −97 dB and increases monotonically to a dotted line maximum 612. Dotted line maximum 612 is located at approximately x-axis 604 frequency of 1 KHz and a corresponding y-axis 602 magnitude of −71 dB. Dotted line low frequency clock signal noise spectrum 610 decreases monotonically from dotted line maximum 612 to x-axis 604 frequency of 20 KHz and a corresponding y-axis 602 magnitude of approximately −130 dB.
A solid line DAC output signal spectrum 614 initiates approximately at a x-axis frequency of 700 KHz and a corresponding y-axis 602 magnitude of −180 dB and increases monotonically to a solid line lower lobe maximum 616. Solid line lower lobe maximum 616 is located at approximately x-axis 604 frequency 800 KHz and a corresponding y-axis 602 magnitude of −175 dB. Solid line DAC output signal spectrum 614 decreases monotonically from solid line lower lobe maximum 616 to approximately x-axis 604 frequency 850 KHz and a corresponding y-axis 602 magnitude of −180 dB. Solid line DAC output signal spectrum 614 increases monotonically from approximately x-axis frequency 850 KHz and y-axis magnitude of −180 dB to a solid line maximum 618. Solid line maximum 618 is located approximately at an x-axis frequency of 1 KHz and y-axis 602 magnitude of −5 dB. Solid line DAC output signal spectrum 614 decreases monotonically from solid line maximum 618 to x-axis frequency 1150 Hz and y-axis magnitude of −180 dB.
Dotted line low frequency clock signal noise spectrum 610 represents the noise frequency spectrum as generated by the conventional circuit of FIG. 2. Dashed line high frequency clock signal noise spectrum represents the noise frequency spectrum as generated by the conventional circuit of FIG. 1. Solid line DAC output signal spectrum 614 represents the signal frequency spectrum as generated by the conventional circuits of FIG. 1 and FIG. 2. The signal-to-noise ratio with dashed line high frequency clock signal noise spectrum 606 is improved over the signal-to-noise ratio with dotted line low frequency clock signal noise spectrum 610. Even though the clock signal jitter generated on reference clock signal 108 by digital oscillator 106 of FIG. 2 is less than the clock signal jitter generated on audio clock signal 112 by audio PLL 110 of FIG. 1, the signal-to-noise ratio for the circuit of FIG. 2 is less than the signal-to-noise ratio for the circuit of FIG. 1.
FIG. 7 is a modification of the conventional circuit shown in FIG. 1 and illustrates a conventional circuit for converting digital audio information to analog using a single PLL for system clock signal and audio clock signal.
A circuit 700 includes elements of FIG. 1 except audio PLL 110 has been removed.
Audio signal generator portion 120 and DAC 130 receive system clock signal 115 generated by system PLL 114.
Audio signal generator portion 120 uses system PLL 114 for synchronizing its operation for generation of digital audio signal 121. Audio signal generator portion 120 processes digital audio information at a speed of execution with respect to system clock signal 115. Typically digital audio information is stored in a compressed format and a function performed by digital audio decompression portion 118 is to convert the compressed digital audio information received on compressed digital audio signal 117 generated by compressed digital audio source 116 into decompressed digital audio information as represented by decompressed digital audio signal 119. The digital information processed by audio signal generator portion 120 is denoted as digital audio signal 121 and is supplied to interpolator 122.
The digital audio information to be supplied by circuit 700 may be of a higher frequency than supplied by audio signal generator portion 120. Interpolator 122 functions to create digital audio information which is an estimate based on digital audio signal 121. For example, the audio information delivered by audio signal generator portion 120 in digital audio signal 121 might be supplied at a rate of 8 KHz. However, the audio information supplied by circuit 700 might be at a rate of 16 KHz. Interpolator 122 may function to insert estimated audio data between each actual audio data.
The output audio information as processed by interpolator 122 is denoted as interpolated signal 124. Interpolated signal 124 is received by noise shaping portion 126. The function of noise shaping portion 126 is to process and move audio noise from one frequency hand to a different frequency band. Typically, noise shaping portion 126 converts audio noise generated in a frequency band which is perceptible by the human ear to audio noise in a frequency band which is less perceptible by the human ear.
The output signal as processed by noise shaping portion 126 is denoted as shaped signal 128. DAC 130 receives shaped signal 128. DAC 130 converts digitized data as received by shaped signal 128 and supplies an analog or continuous electrical signal as denoted as analog signal 132. Analog signal 132 is an output signal as supplied by circuit 700.
Circuit 700 is configured to use a lower performance PLL as denoted by system PLL 114 for driving or clocking DAC 130. The goals of circuit 700 is to remove a costly and power consuming high performance PLL used for driving DAC 130 and replace its function with a PLL used for clocking other circuit portions as denoted by system PLL 114. While the configuration of circuit 700 reduces the cost and power consumption of circuit 700 over other conventional circuit configurations, it also increases the induced jitter noise. The increased jitter noise is a result of using a clock signal with significant clock signal jitter to drive audio signal generator portion 120 and DAC 130. The increased clock signal jitter is a result of using a low quality PLL. As discussed previously, the increased clock signal jitter noise reduces the fidelity of the audio as produced by circuit 700 as compared to a conventional circuit with a lower amount of clock signal jitter noise.
The previous discussion has illustrated the trade-offs involved in the conventional conversion of digital audio information to its analog representation. As illustrated in FIG. 1, the fidelity of a digital-to-analog conversion can be increased by using a high-performance PLL, but at the expense of increased cost and power consumption. As illustrated in FIG. 2, a clock signal generated by a digital oscillator with a lower frequency and lower clock signal jitter may be used to decrease the clock signal jitter noise, but an increase in phase noise is experienced which results in a low fidelity digital-to-analog conversion. As illustrated in FIG. 7, a higher frequency clock signal can be generated from a PLL used for other circuit portions which reduces the associated phase noise, but an increase in clock signal jitter noise by the lower quality PLL produces a low fidelity digital-to-analog conversion. What is needed is a way to perform audio digital-to-analog conversion without using a higher cost and higher power consuming high performance PLL. Furthermore, a method is needed to use existing circuitry in order to prevent higher cost, power consumption and complexity.